1) Field
Embodiments of the present invention pertain to the field of semiconductor processing and, in particular, to local and global reduction of critical dimension (CD) asymmetry in etch processing.
2) Description of Related Art
For pursuing the rapid integration density path of floating gate beyond the 10 nanometer (nm) generation, three-dimensional (3D) NAND devices are considered as the most promising near-term solution. The majority of the solutions presented nowadays use a deposited poly silicon (poly-Si) channel. Vertical NAND (VNAND) relies also on poly-Si channel devices and consists of a charge trapped device (CTF) with a vertical cylindrical geometry. The channel is made of an approximately 10 nm thick deposited poly-Si layer and the integration of such devices has already been proven. Recently, in order to keep a trend of increasing bit density and reducing bit cost of NAND flash memories, three-dimensional Bit-Cost Scalable (BiCS) flash technology has been proposed.
However, improvements are needed in the area of fabrication of VNAND and other three-dimensional based semiconductor structures and devices.